The processing of digital signals is common in many areas of electronics, including audio processing, video processing, data communication, and voice communication. In the real world, the input analog signals are subject to corruption in a variety of ways, such as noise. The conversion of analog signals to digital form includes sampling the analog signal periodically. If converted in a straightforward manner, the corrupted analog signal results in a digital samples which are themselves corrupt (i.e., not representative of the actual received analog signal at the corresponding point in time). The effect of corrupted samples can be mitigated by increasing the sampling frequency and then taking an average of the samples. For example, a system which originally sampled every 1 μs and produced a digital output every 1 μs could be improved by increasing the frequency to 125 ns (0.125 μs), taking 8 samples in the same 1 μs period, and producing, every 1 μs, an average of the 8 samples. However, conventional techniques for designing logic circuits to average digital samples are too slow for this increased sampling frequency, since these techniques rely on adder logic that propagates a carry bit from the least significant bit position to the most significant bit position. Therefore, a need exists to address these and other deficiencies.